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MATLAB and Simulink for System Development on Versal Adaptive SoCs

System designers use MATLAB and Simulink to develop, deploy, and verify designs on Versal™ Adaptive SoC devices. You can use MATLAB and Simulink to:

Model and simulate hardware architectures and algorithms
Deploy systems to Versal Adaptive SoC boards using automatic HDL and C code generation
Debug and verify algorithms running on Versal development boards connected to MATLAB and Simulink test environments

MATLAB and Simulink for System Development on Versal ACAP

Using MATLAB and Simulink for System Development on Versal Adaptive SoC Devices

Early FPGA/SoC Design Verification with Simulink and the Vivado Simulator from AMD Xilinx

Designing AI Engines of Xilinx Versal ACAP Using Simulink and Vitis Model Composer

AMD-Xilinx Versal ACAP Support from SoC Blockset

Simulating Designs for Versal Adaptive SoC Devices

MATLAB and Simulink let you simulate and analyze SoC designs for Versal Adaptive SoC devices. This approach enables you to:

Partition algorithms between portions to execute on Arm^® Cortex^®-A72 processors and implement as IP cores in programmable logic
Incorporate IP cores into preconfigured reference designs and edit the created model to include the algorithm targeted to the processor
Run simulations of hardware or software applications that incorporate the effects of communication between processors, programmable logic, and off-chip DDR memory

Three images include SoC Model Creator screenshot on the left. Simulink top-level model on the top. Simulink software model on the right.

Code Examples

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Designing AI Engines of Xilinx Versal ACAP Using Simulink and Vitis Model Composer (21:00)

Versal AI Core Series VCK190 Evaluation Kit from AMD Xilinx.

Deploying Models to Versal Adaptive SoC Boards

Using SoC Blockset enables you to build software applications and generate IP cores. The blockset also lets you:

Drive the process of generating HDL and C code from Simulink models using HDL Coder and Embedded Coder
Prototype on the Versal AI Core Series VCK190 Evaluation Kit from AMD
Customize models with predefined internal interfaces, external input/output (I/O) interfaces, and AXI4 registers

Code Examples

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Verifying Deployed Algorithms on Versal Adaptive SoC Hardware

You can verify your HDL code with MATLAB and Simulink testbenches rather than writing Verilog or VHDL testbenches. Verifying the code works by using cosimulation with HDL simulators from Siemens^® EDA, Cadence^®, and AMD^®. This process lets you:

Verify and test on the Versal AI Core Series VCK190 Evaluation Kit
Verify IP cores programmed into the fabric of Versal Adaptive SoC devices using FPGA-in-the-loop testing
Test and debug on hardware using MATLAB to access on-board memory with AXI Manager and FPGA Data Capture