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Processor Software

Design and develop the software for the embedded processor component of an SoC application

Create Simulink^® models of the software in an SoC application. Encapsulate the algorithms as a collection of timer-driven and event-driven task subsystems. Define the timing and duration characteristics for tasks.

Blocks

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Task Management

Task Manager	Create and manage task executions in Simulink model (Since R2019a)
Proxy Task	A placeholder for a task in your application (Since R2019b)
Task Trigger	Trigger task execution in your application (Since R2023b)
Task Trigger Merge	Merge multiple task triggers into one trigger (Since R2023b)

Simulation

Task Manager	Create and manage task executions in Simulink model (Since R2019a)
Testbench Task	An external timer-driven task load on your SoC processor application (Since R2019b)
Event Source	Simulate and playback recorded task events (Since R2020b)

Interprocess Data Communication

Interprocess Data Channel	Model interprocessor data channel between two processors (Since R2020b)
Interprocess Data Read	Receive messages from another processor using interprocess communication channel (Since R2020b)
Interprocess Data Write	Send messages to another processor using interprocessor data write (Since R2020b)

Functions

`socTaskTimes`	Plot histogram of the task durations from a recorded Simulation Data Inspector run (Since R2019a)
`socHardwareUsage`	Generate processor core usage statistics from a recorded Simulation Data Inspector run (Since R2021b)
`socTaskSchedulability`	Determine whether set of tasks can be scheduled for specified core assignments (Since R2022b)
`socCreateModel`	Creates a skeleton SoC Blockset model for task set (Since R2022b)

Profiles and Stereotypes

`soc_blockset_profile`	Profile for SoC Blockset systems
`ProcessorCore`	Stereotype for a processor core
`PeriodicSoftwareTask`	Stereotype for a periodic software task
`AperiodicSoftwareTask`	Stereotype for an aperiodic software task

Model Settings

Hardware Implementation Pane

Hardware Mapping Peripherals for Embedded Linux Processors Properties

Hardware Mapping Peripherals for Texas Instruments C2000 Processors Properties

Tools

Hardware Mapping	Map tasks and peripherals in a model to hardware board configurations (Since R2022b)
Performance Report	Display performance and core usage metrics after model simulation or execution on SoC device (Since R2021b)
Simulation Data Inspector	Inspect and compare data and simulation results to validate and iterate model designs

Topics

Design

What is Task Execution?
Learn the SoC Blockset™ definition of task execution and task life-cycle in a processor.
Timer-Driven Task
Create Simulink models with timer-driven task subsystems.
Event-Driven Tasks
Create Simulink models with event driven task subsystems.
Task Duration
Set the execution time or duration of a task in Task Manager block.
Kernel Latency
Specify the kernel response time or latency to start a task execution instance.
Task Management with Schedule Editor
Manage tasks in SoC processor models using the Schedule Editor app.
Value and Caching of Task Subsystem Signals
Signals entering and exiting task subsystems can capture Task Manager block.
Multiprocessor Execution
Configure and run SoC models to simulate a multiprocessor architecture with independent processes.
Run Multiprocessor Models in External Mode
Run a multiprocessor SoC model in external mode running on separate processors on the hardware board.
Interprocess Data Communication via Dedicated Hardware Peripheral
Data communication methods between two or more processes within a single processor or across multiple connected processors.
Design SoC Model Using System Composer
Author, analyze, and transform the architecture of a software system for an SoC device.

Simulation

Task Overruns and Countermeasures
Simulation of task execution experiencing overruns and countermeasures available to either prevent or mitigate overruns.
Task Priority and Preemption
Use Task Manager block to set task priorities and define task execution order with preemption.
Multiprocessor Execution
Configure and run SoC models to simulate a multiprocessor architecture with independent processes.
Data Logging Techniques
Techniques to log processor data from SoC hardware boards.
Task Execution Playback Using Recorded Data
Replay task execution timing using recorded task timing data from previous simulations or processors.

Build and Measurement

Code Generation of Software Tasks
Mapping between tasks in an SoC application model and threads in generated code.
Code Instrumentation Profiler
Use code instrumentation profiling to measure task execution timing on an SoC device.
Kernel Instrumentation Profiler
Use kernel instrumentation profiling to measure task execution timing on an SoC device.
Recording Tasks for Use in Simulation
Task execution timing data and statistics recorded during simulation or from hardware.

Visualization

Task Visualization in Simulation Data Inspector
Visualize the timing and execution states of tasks in the Simulation Data Inspector.
Multicore Execution and Core Visualization
Configure and visualize task execution for single and multicore processor systems.

Featured Examples

Task Execution

Simulate task execution and how to generate code and run it on an SoC hardware board.

Open Script

Scheduling Tasks in SoC Application Design

Schedule application tasks across multiple cores in an SoC Blockset model by using the Schedule Editor tool. Consider an application that has two periodic tasks:

Open Live Script

Scheduling Analysis for Multicore SoC Applications

Maintain real-time rate-monotonic (RM) task scheduling by finding a mapping between application tasks and processor cores. To maintain real-time scheduling, each task must complete within the deadline defined by the period of the task.

Open Live Script

Analyzing Impact of Task Overruns in Control System

Assess stability and performance of an embedded controller in the presence of task overruns.

Open Live Script

Partition Motor Control for Multiprocessor MCUs

Partition real-time motor control application on to multiple processors to achieve design modularity and improved control performance.

Open Script

Audio Beamforming on a Multicore Processor

Implement an audio beamforming application on a multicore processor. To guarantee that the beamforming algorithms execute in real-time, individual beamforming tasks run on different processor cores.

Open Live Script

Determine and Use Task Timing Information

Choose an available method for determining timing information for the tasks on your processor. The Task Manager block uses task timing information to simulate task preemption, overruns, and parallel execution. The accuracy of task timing information provides confidence that the task simulation reflects the actual behavior on your processor.

Open Model

Multicore Implementation of Pulse-Doppler Radar

Implement a pulse-Doppler radar system using multiple processor cores on the Xilinx® Zynq® UltraScale+™ RFSoC evaluation kit. The example builds upon Pulse-Doppler Radar Using Xilinx RFSoC Device that uses a single processor core.

Open Script