Customize the control signals in a SerDes system datapath by adding new custom AMI parameters and using MATLAB® function blocks. This allows you to customize existing control parameters without modifying the built-in blocks in the SerDes Toolbox™ library.

Customize a PassThrough block in Simulink® to use a MATLAB® function block or other Simulink library blocks. You will see how the implementation of a receiver gain or attenuation stage is controlled by an IBIS-AMI parameter, and this example provides a guide to modify PassThrough blocks to implement custom functions for a SerDes system.

Customize a PassThrough Block in Simulink® to implement a CTLE System Object™ with user defined AMI parameters. You can use this example as a guide for modifying PassThrough blocks that leverage system objects. For more information on the purpose of the PassThrough block and an example of using other Simulink library blocks within them, see Customizing Datapath Building Blocks.

Create a custom step response-based CTLE block in Simulink® to model wired communication links of your own specifications. The custom CTLE block exhibits equivalent behavior as the default pole/zero based CTLE block from the SerDes Toolbox™. This example also illustrates:

Simulates a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation. The Simulink® architectural model acts as a high-level specification of the desired analog circuit behavior. Using HDL Verifier™, export the standalone CTLE model into a SystemVerilog behavioral model. The exported model enables early digital control development for analog calibration before you design the analog circuit. A circuit implementation of the CTLE is characterized (offline) using analog simulations. The characterization results are then fed back into the architectural model. This converts the specification-based Simulink model into a circuit-representative model. Both specification and circuit-representative models of the CTLE are provided as part of this example. Use HDL Verifier to regenerate the SystemVerilog behavioral model. This model can be used for mixed-signal validation; turning the specification-based SystemVerilog model into a circuit-representative SystemVerilog model. This automation keeps the architectural, behavioral, and circuit models in synchronicity.

Demonstrates a work flow to simulate a continuous-time linear equalizer (CTLE) in several design domains, while keeping the underlying models in synchronization through tool automation.

Use a time-interleaved analog to digital converter (ADC) from Mixed-Signal Blockset™ to develop an offset and gain calibration engine for mismatched interleaved ADC paths. For an architectural representation of time-interleaved ADC for IBIS-AMI export, see the ADC IBIS-AMI Model based on COM and Architectural 112G PAM4 ADC-Based SerDes Model examples.