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Code Generation Fundamentals

HDL code generation startup, language selection, HDL code generation scripts

The Filter Design HDL Coder™ workflow automates the implementation of filter designs in HDL. First, design a filter, either manually or by using DSP System Toolbox™ tools Filter Designer or Filter Builder. Then, use the Generate HDL dialog box or the generatehdl function to configure code generation options and generate a VHDL or Verilog implementation of the design. This workflow enables you to fine-tune algorithms and models through rapid prototyping and experimentation, while spending less time on HDL implementation. See Starting Filter Design HDL Coder.

Functions

`fdhdltool`	Open Generate HDL dialog box
`generatehdl`	Generate HDL code for quantized filter

Properties

Fundamental HDL Code Generation Properties

Customize filter name, destination folder, and specify target language

Topics

Starting Filter Design HDL Coder
Access the Filter Design HDL Coder tool.
Selecting Target Language
Select your target language. HDL code is generated in either VHDL or Verilog.
Generating HDL Code
Once your filter design and HDL settings are ready, generate HDL code for your design.
Capturing Code Generation Settings
To save your code generation settings, you can generate a script that includes the options you selected.
Closing Code Generation Session
Save your parameter settings before closing the session.
Generate HDL Code for Filter System Objects
Learn about the specifics of HDL code generation from filter System objects.
Supported Filter System Objects
You can generate HDL code for filter System objects from DSP System Toolbox™.

Featured Examples

HDL Video Filter

Illustrates how to generate HDL code for an ITU-R BT.601 luma filter with 8-bit input data and 10-bit output data. This filter is a low-pass filter with a -3 dB point of 3.2 MHz with a 13.5 MHz sampling frequency and a specified range for both passband ripple and stopband attenuation shown in the ITU specification. The filter coefficients were designed using the DSP System Toolbox™. This example focuses on quantization effects and generating HDL code for the System object filter.

Open Live Script

HDL Digital Up-Converter (DUC)

Illustrates how to generate HDL code for a Digital Up-Converter (DUC). A DUC is a digital circuit which converts a digital baseband signal to a passband signal. The input baseband signal is sampled at a relatively low sampling rate, typically the digital modulation symbol rate. The baseband signal is filtered and converted to a higher sampling rate before modulating a direct digitally synthesized (DDS) carrier frequency.

Open Live Script

HDL Sample Rate Conversion Using Farrow Filters

Design and implement hardware efficient sample rate converters for an arbitrary factor using polynomial-based (Farrow) structures. Sample rate conversion (SRC) between arbitrary factors is useful for many applications including symbol synchronizations in digital receivers, speech coding, audio sampling, etc. This example shows how you can convert the sampling rate of an audio signal from 8kHz to 44.1 kHz.

Open Live Script