Test and verify Verilog^® and VHDL^® designs for FPGAs, ASICs, and SoCs with HDL Verifier™. Verify RTL with testbenches running in MATLAB^® or Simulink^® using cosimulation with HDL simulators. Use these same testbenches with FPGA and SoC development boards to verify HDL implementations in hardware.

HDL Verifier generates SystemVerilog verification models for use in RTL testbenches, including Universal Verification Methodology (UVM) testbenches. These models run natively in simulators from Siemens^®, Cadence^®, Synopsys^®, and Xilinx^® via the SystemVerilog Direct Programming Interface (DPI).

HDL Verifier provides tools for debugging and testing FPGA implementations on Xilinx, Intel^®, and Microchip boards. You can use MATLAB to write to and read from memory-mapped registers for testing designs on hardware. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.