Learn how to deploy your Simulink^® model of FOC algorithms on the Xilinx^® Zynq^® UltraScale+ module from the Trenz Electronic motor development kit. Using HDL Workflow Advisor, discover how to automatically generate:

1. HDL IP core and AXI hardware interface components from your Simulink model or subsystem
2. FPGA bitstreams, which are required for deploying your design on the hardware logic of the Zynq SoC
3. Software interface executables to run on the ARM processor of the Zynq SoC