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Deep Learning HDL Toolbox

Prototype and deploy deep learning networks on FPGAs and SoCs

Deep Learning HDL Toolbox™ provides functions and tools to prototype and implement deep learning networks on FPGAs and SoCs. It provides pre-built bitstreams for running a variety of deep learning networks on supported Xilinx^® and Intel^® FPGA and SoC devices. Profiling and estimation tools let you customize a deep learning network by exploring design, performance, and resource utilization tradeoffs.

Deep Learning HDL Toolbox enables you to customize the hardware implementation of your deep learning network and generate portable, synthesizable Verilog^® and VHDL^® code for deployment on any FPGA (with HDL Coder™ and Simulink^®).

Deep Learning Inference on FPGAs

Prototype and implement deep learning networks on FPGAs for edge deployment.

Programmable Deep Learning Processor

The toolbox includes a deep learning processor that features generic convolution and fully-connected layers controlled by scheduling logic. This deep learning processor performs FPGA-based inferencing of networks developed using Deep Learning Toolbox™. High-bandwidth memory interfaces speed memory transfers of layer and weight data.

Deep Learning Processor Architecture

Currently Supported Networks and Layers

The deep learning processor contains generic convolution and fully-connected processing modules that are programmed to execute the specified network.

Deep learning processor architecture.

Compilation and Deployment

Compile your deep learning network into a set of instructions to be run by the deep learning processor. Deploy to the FPGA and run prediction while capturing actual on-device performance metrics.

Deploy Transfer Learning Network for Lane Detection

Compare AlexNet, VGG-19, or DarkNet-19 for Image Classification on an FPGA

Vehicle Detection Using YOLO v2 on FPGA

Compile your deep learning network into a set of instructions to be deployed to the deep learning processor.

Compiling and deploying a YOLO v2 network.

Get Started with Prebuilt Bitstreams

Prototype your network without FPGA programming using available bitstreams for popular FPGA development kits.

Try Deep Learning on FPGA with Only Five Additional Lines of MATLAB Code

Xilinx FPGA and SoC Support from Deep Learning HDL Toolbox

Intel FPGA and SoC Support from Deep Learning HDL Toolbox

Use MATLAB to Prototype Deep Learning on a Xilinx FPGA

FPGA-Based Inferencing in MATLAB

Run deep learning inferencing on FPGAs from MATLAB.

Creating a Network for Deployment

Begin by using Deep Learning Toolbox to design, train, and analyze your deep learning network for tasks such as object detection or classification. You can also start by importing a trained network or layers from other frameworks.

Transfer Learning Using AlexNet

Create Simple Deep Learning Network for Classification

Deep Learning Import, Export, and Customization

Deep Learning with MATLAB: Transfer Learning in 10 Lines of MATLAB Code

Deploying Your Network to the FPGA

Once you have a trained network, use the deploy command to program the FPGA with the deep learning processor along with the Ethernet or JTAG interface. Then use the compile command to generate a set of instructions for your trained network without reprogramming the FPGA.

Get Started with Deep Learning FPGA Deployment on Xilinx ZCU102 SoC over Ethernet

Get Started with Deep Learning FPGA Deployment on Intel Arria 10 SoC over JTAG

Fast Ethernet-Based Based Deployment

Using MATLAB to configure the board and interface, compile the network, and deploy to the FPGA.

Use MATLAB to configure the board and interface, compile the network, and deploy to the FPGA.

Running FPGA-Based Inferencing as Part of Your MATLAB Application

Run your entire application in MATLAB^®, including your test bench, preprocessing and post-processing algorithms, and the FPGA-based deep learning inferencing. A single MATLAB command, predict, performs the inferencing on the FPGA and returns results to the MATLAB workspace.

Custom Trained Defect Detection Network

Deploy Transfer Learning Network for Lane Detection

MATLAB loop that captures an image, preprocesses it by resizing for AlexNet, runs deep learning inferencing on the FPGA, and then post-processes and displays the results.

Run MATLAB applications that perform deep learning inferencing on the FPGA.

Network Customization

Tune your deep learning network to meet application-specific requirements on your target FPGA or SoC device.

Profile FPGA Inferencing

Measure layer-level latency as you run predictions on the FPGA to find performance bottlenecks.

Profile Inference Performance on FPGA

Profile Logonet on Intel Arria 10 SoC

Deep learning inference profiling metrics.

Profile deep learning network inference on an FPGA from MATLAB.

Tune the Network Design

Using the profile metrics, tune your network configuration with Deep Learning Toolbox. For example, use Deep Network Designer to add layers, remove layers, or create new connections.

Interactively Build, Visualize, and Edit Deep Learning Networks (3:54)

Use Only the Convolution Layers from the Resnet-50 Network on an FPGA

Deep Network Designer

Prototype and Adjust a Deep Learning Network on FPGA

Deep Learning Quantization

Reduce resource utilization by quantizing your deep learning network to a fixed-point representation. Analyze tradeoffs between accuracy and resource utilization using the Model Quantization Library support package.

Deep Learning Fixed-Point Quantization

What Is int8 Quantization and Why Is It Popular for Deep Neural Networks?

Classify Images on an FPGA Using a Quantized DAG Network

Deep Network Quantization and Deployment Using Deep Learning Toolbox Model Quantization Library

Deploying Custom RTL Implementations

Deploy custom RTL implementations of the deep learning processor to any FPGA, ASIC, or SoC device with HDL Coder.

Custom Deep Learning Processor Configuration

Specify hardware architecture options for implementing the deep learning processor, such as the number of parallel threads or maximum layer size.

Custom Processor Configuration Workflow

Deep Learning Import, Export, and Customization

Generate HDL for a Deep Learning Processor

Generate Synthesizable RTL

Use HDL Coder to generate synthesizable RTL from the deep learning processor for use in a variety of implementation workflows and devices. Reuse the same deep learning processor for prototype and production deployment.

Configure and Generate Custom Deep Learning Processor

Generate Custom Bitstream

The dlhdl.BuildProcessor class generates synthesizable RTL from the custom deep learning processor.

Generate synthesizable RTL from the deep learning processor.

Generate IP Cores for Integration

When HDL Coder generates RTL from the deep learning processor, it also generates an IP core with standard AXI interfaces for integration into your SoC reference design.

Getting Started with Hardware-Software Co-Design Workflow for Xilinx Zynq UltraScale+ MPSoC Platform

Getting Started with Hardware-Software Co-Design Workflow for Intel SoC Devices