Introduction

The model in this example generates a baseband waveform specified by 3GPP TS 36.211. The waveform includes the primary synchronization signal (PSS), secondary synchronization signal (SSS), cell-specific reference signals (CRS), and the master information block (MIB) for transmission through the physical broadcast channel (PBCH) for multiple antennas. The model supports dynamic change of NCellID and NDLRB. The MIMO transmitter design is optimized for HDL code generation and when implemented on an FPGA, it can be used to transmit MIMO signals in real time over the air. The MIMO design aids the decoding process in the presence of LTE fading channel. This example supports 1, 2, or 4 antennas and uses transmit diversity as specified in the [ 1 ].

The architecture presented in this example is extensible and allows for integration of additional physical transmission channels such as physical downlink control channel (PDCCH), physical downlink shared channel (PDSCH), physical control format indicator channel (PCFICH), and physical HARQ indicator channel (PHICH).

Architecture and Configuration

This figure shows the LTE HDL Transmitter architecture with PSS, SSS, CRS, and PBCH transmission chains.

The input sampling rate is assumed to be at 10.24 MHz. PSS, SSS, PBCH, and CRS signals are generated in parallel, based on the input configuration. A single stream of PSS and SSS signals is used for all the antennas. Multiple streams of PBCH data are generated for multiple antennas through the layer mapping and precoding stages. Each antenna is associated with a corresponding LTE memory bank, which is sized to store one subframe of LTE data samples. These generated data streams are written into LTE memory bank corresponding to indices generated, based on the output ready signal of LTE OFDM Modulator. Then, the data is read out of all LTE memory bank in parallel, modulated and transmitted on the antennas simultaneously. The LTE OFDM Modulator block uses a 2048-point FFT to support all NDLRBs.

In this example, the transmitter transmits LTE MIMO signals for the following configurations:

        Property              Value       
    ________________    __________________

    Duplex mode         FDD               
    CellRefP            1/2/4             
    Bandwidth           1.4 - 20 MHz      
    Cyclic prefix       Normal/Extended   
    Initial subframe    0                 
    Initial frame       0                 
    Ng                  Sixth/Half/One/Two
    PHICH duration      Normal/Extended   

Structure of Example Model

The top level structure of the ltehdlTransmitter model is shown below. You can generate HDL code for the HDL LTE MIMO Transmitter subsystem.

Input start is a pulse signal to trigger the transmission. You can configure other parameters, including NDLRB, NCellID, Cyclic prefix, Ng, PHICH duration and CellRefP in the workspace after loading or opening the ltehdlTransmitter.slx model. The ltehdlTransmitter_init.m script is executed automatically by the model's InitFcn callback. This script configures the individual blocks in the HDL LTE MIMO Transmitter subsystem. The default transmitter configuration used by the ltehdlTransmitter_init.m script is:

enb.NDLRB = 6;                      % {6,15,25,50,75,100}

enb.CyclicPrefix = 'Normal';        % {'Normal','Extended'}

enb.Ng = 'Sixth';                   % {'Sixth','Half','One','Two'}

enb.PHICHDuration = 'Normal';       % {'Normal','Extended'}

enb.CellRefP = 4;                   % {1,2,4}

tx_cellids = [390 89 501 231 500];  % {0 to 503}

outRate = 1;                        % {1,2}

TotalSubframes = 45;                % {positive integer}

This default configuration can be changed to use other possible values for each variable, as noted in the comment on each line.

HDL LTE MIMO Transmitter

The structure of the HDL LTE MIMO Transmitter subsystem is shown below. The Frame Controller controls the subframe and frame indices. The Input Sampler samples the inputs NDLRB and NCellID and then propagates the values to the subsequent blocks. The PSS & SSS generation generates PSS, SSS, and the corresponding memory address based on NDLRB and subframe index. The MIB generation block generates the serial MIB data. The BCH Encoder and PBCH Encoder generate information for PBCH channel and memory addresses for all the antennas. The CellRS Chain generates cell-specific reference signals and corresponding addresses for each antenna. The Read Write Logic writes and reads the grid data from each LTE Memory Bank and provides the data to the corresponding LTE OFDM Modulator. The Discrete FIR Filter block filters the modulated data using coefficients that are calculated based on the input configuration.

Frame Controller

This subsystem assumes an input sampling rate of 10.24 MHz. It controls the subframe and radio frame boundaries by providing cellEnb signal to sample NCellID. It returns radio frame and subframe indices. It also provides syncStart, bchStart, and cellRSStart trigger signals to control the downstream blocks.

PSS & SSS Generation

This subsystem generates the primary synchronization signal (PSS), secondary synchronization signal (SSS), and respective write addresses for LTE Memory Bank based on inputs NDLRB and NCellID. syncStart triggers the generation of PSS and SSS. The PSS and SSS occupy the same central 62 subcarriers of two OFDM symbols in a resource grid [ 1 ]. This subsystem generates both the signals and their corresponding addresses at the same time, so that a single stream of both PSS and SSS can be written to all the LTE Memory Banks corresponding to each antenna simultaneously.

The PSS sequence is generated from a frequency-domain Zadoff-Chu sequence [ 1 ]. The Zadoff-Chu root sequence index depends on NCellID2, which is derived from NCellID. There are three possible NCellID2 values, so all possible PSS sequences are precalculated and stored in PSS_LUT.

The SSS sequence is an interleaved concatenation of two 31-bit length binary sequences. The concatenated sequence is scrambled with a scrambling sequence given by PSS. The combination of these sequences differs between subframe 0 and subframe 5 [ 1 ]. The indices m0 and m1 are derived from the physical-layer cell identity group, NCellID1 [ 1 ]. These indices and the sequences s(n), c(n), and z(n) are calculated and stored in m0_LUT, m1_LUT, S_LUT, C_LUT, and Z_LUT respectively.

BCH Encoder

Broadcast Channel (BCH) processes the MIB information arriving to the block in the form of a maximum of one transport block for every transmission time interval (TTI) of 40 ms. The block implements the following coding steps.

PBCH Encoder

The physical broadcast channel processes the coded bits in the following steps.

The subsystem shown generates the output sequence for 4 antennas as specified in [ 1 ].

CellRS Chain

The cell-specific reference sequence is complex modulated values of a pseudo-random sequence as defined in [ 1 ]. The pseudo-random sequence generator is initialized with at the start of each OFDM symbol,as specified in [ 1 ].

Read Write Logic

The Read Write Logic subsystem contains a Write Selector, Read Selector, four LTE Memory Banks with a Grid Bank Select associated with each of the LTE Memory Bank. The LTE Memory Bank storage capacity is one subframe of complex modulated symbols at the largest supported LTE bandwidth (20 MHz). Each LTE Memory Bank can store 14 x 2048 x 16-bit complex values, that is, 14 OFDM symbols, each containing 2048 complex values.

The Write Selector writes subframes of data into the memory banks. The PSS and SSS occupy central subcarriers. A single stream of PSS and SSS data is used for all the antennas. The PBCH data consists of multiple streams corresponding to each antenna port. The CRS data generated is mapped to the grid based on the four addresses generated for each LTE Memory bank in CellRS_indices block. The Write Selector first writes PSS and SSS simultaneously into corresponding locations in all LTE Memory Banks. Then, it writes PBCH data and CRS data into the corresponding LTE Memory Banks and returns rd_enb to indicate that the write is complete.

The Read Selector reads the samples from each LTE Memory Bank based on rd_enb and ready from the LTE OFDM Modulator block. Each LTE Memory Bank returns a 14 element vector corresponding to a single subcarrier. The Grid Bank Select selects the appropriate sample from the 14 element vector to form the resource grid output for each antenna.

Since the scope of this example is limited to PSS, SSS, CRS, and PBCH transmission, all the LTE Memory Banks are erased at the start of every subframe, before writing new data into the memory.

OFDM Modulation and Filtering

Grid data from LTE Memory Bank is OFDM-modulated using the LTE OFDM Modulator block with 'Output data sample rate' parameter set to 'Match output data sample rate to NDLRB'. The modulated data is filtered using a Discrete FIR Filter block with coefficients generated at a sampling rate corresponding to the NDLRB. Variant subsystems control the number of OFDM modulators and FIR filters used based on the number of antennas, which reduces the resource utilization when a single antenna is used.

Verification and Results

After running the simulation, the ltehdlTransmitter_PostSim.m script is executed automatically by the StopFcn callback of the model. In this example, the transmitter output is verified by the following methods:

Verification of model's transmitted signal:

The transmitter output signal in this model is cross-verified with a reference transmitter signal that is generated using LTE Toolbox™ functions by the following two subplots for each antenna.

Cell Search & MIB Decoding Results:

The valid samples of the transmitter output signal are stored to the workspace variable txSamples. These samples are passed through an LTE fading channel to create the receiver input signal, rxSamples. The lteFadingChannel (LTE Toolbox) function models the LTE fading channel.

This example uses the following channel configuration:

chcfg.NRxAnts = 1;
chcfg.MIMOCorrelation = 'Medium';
chcfg.NormalizeTxAnts = 'On';
chcfg.DelayProfile = 'EPA';               % {'off','EPA'}
% The below model configuration exist only if Delay profile is not set
% to 'off'.
chcfg.DopplerFreq = 5;
chcfg.SamplingRate = 30.72e6;
chcfg.InitTime = 0;
chcfg.NTerms = 16;
chcfg.ModelType = 'GMEDS';
chcfg.NormalizePathGains = 'On';
chcfg.InitPhase = 'Random';
chcfg.Seed = 1;

To create a fading-free channel, set the chcfg.DelayProfile to 'off' in the ltehdlTransmitter_PostSim.m script.

This channel configuration works with the default enb structure, and supports changes only in the enb.PHICHDuration and enb.Ng fields.

The following figures show the results of the cell search and MIB decoding of the channel output, rxSamples, using LTE toolbox™ functions. These figures verify the transmitter performance and compare the HDL transmitter implementation against the input configuration defined in tx_cellids and enb.

The example model does not support simulation in rapid accelerator mode.

Validation with Cell Search and MIB Recovery Example

You can verify the LTE HDL PBCH Transmitter example by connecting it to the LTE HDL MIB Recovery example model and checking that the output of the transmitter is decoded correctly. To make the transmitter model compatible with the receiver model, make these changes to the transmitter:

The figure shows the HDL LTE MIMO Transmitter and HDL LTE MIB Recovery subsystems connected together. It also shows the result of simulating the model. The display blocks show the CellID and MIB fields (NDLRB, Ng, PHICH duration and System Frame Number (SFN)) that the receiver decoded from the output of the HDL LTE MIMO Transmitter subsystem.

You can also verify the design without using a channel by terminating the output from the second antenna and bypassing the channel system with the output from the first antenna.

HDL Code Generation

To check and generate HDL for this example, you must have an HDL Coder™ license. Use the makehdl and makehdltb commands to generate the HDL code and test bench for the HDL LTE MIMO Transmitter subsystem. Because the stopTime in this example depends on TotalSubframes, the test bench generation time depends on the TotalSubframes.

The HDL LTE MIMO Transmitter subsystem is synthesized on a Xilinx® Zynq®-7000 ZC706 evaluation board. The post place and route resource utilization results are shown in the table below.

         Resources          No. of antennas used = 1    No. of antennas used = 2    No. of antennas used = 4
    ____________________    ________________________    ________________________    ________________________

    Slice Registers                  12788                       23839                       45787          
    Slice LUT                        11984                       22220                       42861          
    RAMB36                           41                          82                          164            
    RAMB18                           11                          21                          41             
    DSP                              49                          93                          177            
    Max. Frequency (MHz)             210.08                      206.39                      204.75         

References