Model Architecture

This section explains the high-level architecture of the DVB-S2 receiver model. The Synchronization and PLHeader Recovery block extracts the data symbols, estimates noise variance, and decodes physical layer (PL) header information from the Rx Input Waveform signal. The Symbol Demodulator block demodulates the data symbols and computes soft bits. The Deinterleaver block deinterleaves and FEC Decoder block decodes the soft bits to extract a DVB-S2 baseband frame signal. The Stream Recovery block extracts the BB header information and the output stream bits from the baseband frame.

This block diagram shows the high-level architecture of the model.

File Structure

This example uses four Simulink models, five MATLAB files, and one Simulink data dictionary.

System Interface

This figure shows the top-level overview of the dvbs2hdlReceiver.slx model.

Model Inputs

Model Outputs:

Model Structure

This figure shows the top-level model of the DVB-S2 HDL Receiver subsystem. The subsystem comprises three model references, dvbs2hdlSyncPLHeaderRecoveryCore, dvbs2hdlBBFrameRecoveryCore, and dvbs2hdlStreamRecoveryCore.

dvbs2hdlSyncPLHeaderRecoveryCore — Synchronizes the input receiver waveform, estimates noise variance, and decodes PL header information. For more information, see DVB-S2 HDL PL Header Recovery example.

dvbs2hdlBBFrameRecoveryCore — Demodulates the input symbols using DVB-S2 Symbol Demodulator block to extract soft bits, deinterleave the soft bits using DVB-S2 DeinterLeaver subsystem, and FEC decodes (LDPC and BCH decodes) the soft bits using the DVB-S2 LDPC Decoder block and the DVB-S2 BCH Decoder block to extract baseband frame (BBFrame). The baseband frame streams into the dvbs2hdlStreamRecoveryCore model reference.

The DVB-S2 Deinterleaver subsystem in the dvbs2hdlBBFrameRecoveryCore model reference continuously stores the soft bits received from the DVB-S2 Symbol Demodulator inside the RAM subsystem. The RAM Address Generator subsystem generates the read and write logic to the RAM for deinterleaving.

In the RAM Address Generator subsystem, the nRows and nColumns subsystem stores the number of rows and columns of each of the possible configuration in look-up tables (LUT). Based on the PL header parameters, the number of rows and columns is decided for deinterleaving. The Read Offset Address subsystem generates the deinterleaver indices of each frame as an offset address. The Generate and Add Read Base Address subsystem adds the offset address with a base read address to get the actual address of the soft-bit stored in the RAM. The Parameter Store FIFO subsystem stores the PL header parameters and reads these parameters in synchronous with start of each frame.

This table shows the rows and columns considered for deinterleaving for each of the configurations.

    Modulation    Rows (Normal)    Rows (Short)    Columns
    __________    _____________    ____________    _______

     QPSK             64800           16200           1   
     8-PSK            21600           5400            3   
     16-APSK          16200           4050            4   
     32-APSK          12960           3240            5   

dvbs2hdlStreamRecoveryCore — Decodes the BB header and recovers the stream bits. The BB Descrambler subsystem descrambles the baseband frame. The BB Demultiplexer subsystem demultiplexes the descrambled frame into BB header and data bits. The BB Header CRC Check subsystem uses the General CRC Syndrome Detector HDL Optimized block to check the CRC status and discards the baseband frames that fails CRC check. The BB Decoder subsystem extracts the BB header information and the data field. For packetized stream of bits, the control signals are generated to indicate the start, end, and validity of bits for each packet. The General CRC Syndrome Detector HDL Optimized block checks the CRC status of each packet. For continuous stream of bits, the data field is passed on to the output.

Run the Model

Set the symbol rate, MODCOD, FECFrame type values, input stream format, user packet length and channel impairments on the mask of the Input Configuration subsystem and run the dvbs2hdlReceiver model. Alternatively, to run the model, execute this command at the MATLAB command window.

sim dvbs2hdlReceiver

The MODCOD value must be a row vector. Each element of the row vector corresponds to a frame.

Note: Use QPSK modulated frames initially to achieve time frequency and phase synchronization.

Verification and Results

Run the dvbs2hdlReceiver.slx model. The model utilizes 120 short QPSK frames for synchronization.

### Starting serial model reference simulation build.
### Successfully updated the model reference simulation target for: dvbs2hdlBBFrameRecoveryCore
### Successfully updated the model reference simulation target for: dvbs2hdlStreamRecoveryCore
### Successfully updated the model reference simulation target for: dvbs2hdlSyncPLHeaderRecoveryCore

Build Summary

Simulation targets built:

Model                             Action                        Rebuild Reason                                               
=============================================================================================================================
dvbs2hdlBBFrameRecoveryCore       Code generated and compiled.  dvbs2hdlBBFrameRecoveryCore_msf.mexw64 does not exist.       
dvbs2hdlStreamRecoveryCore        Code generated and compiled.  dvbs2hdlStreamRecoveryCore_msf.mexw64 does not exist.        
dvbs2hdlSyncPLHeaderRecoveryCore  Code generated and compiled.  dvbs2hdlSyncPLHeaderRecoveryCore_msf.mexw64 does not exist.  

3 of 3 models built (0 models already up to date)
Build duration: 0h 8m 2.842s


Number of frames synced = 124 out of 124
Initial frames not compared = 120
Number of frames lost due to BB Header CRC failure = 0 out of 4
Number of packets lost due to packet CRC failure = 0 out of 27

HDL Code Generation

To generate the HDL code for this example, you must have HDL Coder™. Use makehdl and makehdltb commands to generate HDL code and HDL testbench for the DVB-S2 HDL Receiver subsystem. The testbench generation time depends on the simulation time.

The resulting HDL code is synthesized for a Xilinx® Zynq® UltraScale+ RFSoC ZCU111 board. The post place and route resource utilization are shown in this table. The maximum frequency of operation is 235 MHz.

      Resources      Usage
    _____________    _____

    CLB LUT          79559
    CLB Registers    91841
    RAMB36           314  
    RAMB18           46   
    DSP48            298  

References