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HDL Code Generation and Deployment

Generate HDL code using HDL Coder™, verify using HDL Verifier™, and prototype using hardware support packages

Wireless HDL Toolbox™ provides blocks that support HDL code generation. To generate HDL code from designs that use these blocks, you must have an HDL Coder license. HDL Coder also enables you to generate scripts and test benches for use with third-party HDL simulators.

If you have an HDL Verifier license, you can use the FPGA-in-the-loop (FIL) feature to prototype your HDL design on an FPGA board. The FIL blocks provide efficiency improvements for streaming data across the interface between Simulink^® and the FPGA board. HDL Verifier also enables you to cosimulate a Simulink model with an HDL design running in a third-party simulator.

To design, prototype, and verify practical wireless communications systems on hardware, download hardware support packages such as Communications Toolbox™ Support Package for Xilinx^® Zynq^®-Based Radio.

Blocks

FIL Frame To Samples	Convert frame-based data to sample stream for FPGA-in-the-loop
FIL Samples To Frame	Convert sample stream from FPGA-in-the-loop to frame-based data

Topics

HDL Code Generation Support
Find supported blocks, and implement streaming interface in HDL.
Generate HDL Code
Generate HDL code from Simulink subsystems.
FPGA-in-the-Loop
Real-time design verification of communications systems with FPGAs.
HDL Verifier Cosimulation Model Generation in HDL Coder (HDL Coder)
This example shows how to reuse an existing Simulink® model to verify HDL Coder™ generated hardware designs using an HDL Verifier™ cosimulation test bench.
Prototype Wireless Communications Algorithms on Hardware
Prototype Wireless HDL Toolbox designs on Xilinx Zynq-based boards using hardware support packages.