Main Content

Multiprocessor Architecture Modeling

Design, evaluate, and implement multiprocessor architecture modeling

Partition algorithms for multicore execution with inter-processor data communication (IPC) and co-processor (control law accelerator) blocks. With processor-in-the-loop (PIL) simulation, you can cross-compile source code on your development computer, and then download and run the object code on the processor in the hardware board.

Map tasks and peripherals in a model to hardware board configurations using Hardware Mapping tool.

Blocks

expand all

CLA Task ManagerCreate and manage task executions in Control Law Accelerator (CLA) model (Since R2022a)
Software Trigger CPU<->CLATrigger software events between processor (CPU) and control law accelerator (CLA) (Since R2022a)
ADC InterfaceConvert analog signal on ADC input pin to digital signal (Since R2020b)
PWM InterfaceSimulate pulse width modulation (PWM) output from hardware (Since R2020b)
Interprocess Data ChannelModel interprocessor data channel between two processors (Since R2020b)
Interprocess Data ReadReceive messages from another processor using interprocess communication channel (Since R2020b)
Interprocess Data WriteSend messages to another processor using interprocessor data write (Since R2020b)
Task ManagerCreate and manage task executions in Simulink model (Since R2019a)

Tools

SoC BuilderBuild, load, and execute SoC model on SoC, FPGA, and MCU boards (Since R2019a)
Hardware MappingMap tasks and peripherals in a model to hardware board configurations (Since R2022b)

Topics

Processor-in-Loop (PIL) Simulation

  • PIL Simulation
    Processor-in-the-Loop (PIL) simulation techniques for Texas Instruments hardware board.

Multiprocessor Modeling