bat365 Homepage

UVM Generation

Generate UVM components from Simulink^® subsystems

Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.

Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.
Generate UVM test components, and integrate them into your existing UVM environment.

To use this functionality, download and install the ASIC Testbench for HDL Verifier add-on. This feature also requires Simulink Coder™.

Functions

uvmbuild Generate UVM test bench from Simulink model (Since R2019b)

Blocks

Sequence Feedback

Connect between scoreboard and sequence in UVM test bench model (Since R2023a)

Objects

`uvmcodegen.uvmconfig`	UVM configuration object (Since R2020b)
`svdpiConfiguration`	Configure workflows for UVM and SystemVerilog component generation from MATLAB (Since R2023a)

Topics

UVM Component Generation Overview
Generate a Universal Verification Methodology (UVM) environment from a Simulink model.
Customize Generated UVM Code
Customize file banners and HDL simulation timescale when generating a UVM test bench.
Generate SystemVerilog Assertions and Functional Coverage
Generate SystemVerilog immediate assertions from verify statements and model verification blocks, and collect functional coverage information (requires Simulink Test™ license).
Use Tunable Parameters to Generalize UVM Simulation
Generate UVM parameters from Simulink tunable parameters.
Tunable Parameters in Sequence Subsystem
Generate random constraint parameters in UVM sequence from Simulink tunable parameters.
Tunable Parameters in Scoreboard Subsystem
Generate random constraint parameters in UVM scoreboard from Simulink tunable parameters.
SystemVerilog and UVM Template Engine
Generate customizable SystemVerilog modules and UVM components from MATLAB using templates.
Template Engine Language Syntax
Template variable definition and usage.
Generate Cross-Platform UVM Components
Generate the UVM components for a Linux^® operating system from your Windows^® host machine.

Featured Examples

Use Templates to Create SystemVerilog DPI and UVM Components

Generate SystemVerilog direct programming interface (DPI) and universal verification methodology (UVM) components from MATLAB® functions using built-in templates. This example also reviews the generated SystemVerilog and how it relates to the template. This example teaches you basic template capabilities, that you can use to create a custom template.

Open Live Script

Generate Parameterized UVM Testbench from Simulink

Develop a design and testbench in Simulink® and generate an equivalent simulation for a universal verification methodology (UVM) environment using uvmbuild. You can then extend this testbench to refine your verification using protocol-specific drivers, constrained random sequences, and parameterized scoreboards.

Open Live Script

Replace Behavioral DUT with RTL DUT in UVM Testbench

Move from a stand-in C-based design DUT to a simple behavioral RTL DUT interface to a full protocol-based RTL DUT interface that uses AXI4-Lite and AXI4-Stream bus protocols. Several of the UVM components must change, such as the driver and monitor, but you can use reuse the original testbench structure and the sequence and scoreboard components without modification.

Open Live Script

Add Random Constraints to Sequences in UVM Testbench

Add constrained random verification to a universal verification methodology (UVM) test bench generated from Simulink®. Both Simulink parameters and input ports to the stimulus generation results in randomizable sequence class data members in the UVM test bench. Through standard UVM class inheritance and factory overrides, the design verification engineer can add new and valuable constrained random test cases to their UVM test suite.

Open Live Script

Change Parameters and Coverage Goals of Scoreboard in UVM Testbench

Control the parameters of the response checker in a UVM testbench generated from Simulink®. Such parameterization helps the design verification engineer reuse the scoreboard under different testing scenarios. Simulink parameters to the checker will result in a configuration object whose values can be set in a derived test class (randomized or not) or directly via a command line plusarg.

Open Live Script

Include Driver and Monitor in UVM Test Bench

Uses the uvmbuild function to generate a Universal Verification Methodology (UVM) test bench, which includes a UVM driver and monitor from a Simulink® design and test bench.

Open Live Script

Integrate SystemVerilog DPI into UVM Framework Workflow

Generate reusable verification components from a Simulink® model as SystemVerilog DPI components using HDL Verifier™ software. You use the MATLAB-to-UVMF (mtlb2uvmf) workflow to create Universal Verification Methodology (UVM) test benches quickly. For more information on mtlb2uvmf workflow, see bat365® Integration from Siemens Verification Academy.

Open Live Script