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FPGA Data Capture

Capture signal data from live FPGA

Use FPGA data capture to observe signals from your design while the design is running on the FPGA. This feature captures a window of signal data from the FPGA and returns the data to MATLAB^® or Simulink^®. To capture the signals, HDL Verifier™ generates an IP core that you must integrate into your HDL project and deploy to the FPGA along with the rest of your design. HDL Verifier also generates an app, System object™, and Simulink model that communicate with the FPGA and return the data to MATLAB or Simulink.

To capture FPGA data:

Generate customized components and an IP core. Specify port names and sizes for the generated IP. These ports connect to the signals you want to capture, and the signals you want to use as triggers to control when the capture occurs.
Integrate the generated IP into your FPGA design and deploy the design to your FPGA board. This step is automated when using HDL Workflow Advisor.
Use the generated app, System object, or Simulink model to capture data for analysis, verification, or display. You can configure a trigger condition to control when the capture occurs and a capture condition to control which data to capture.

To use this feature, you must download a hardware support package for your FPGA board. See documentation for support packages. For an Intel^® FPGA board, see FPGA Data Capture. For a Xilinx^® FPGA board, see FPGA Data Capture.

For information on downloading support packages, see Download FPGA Board Support Package.

Apps

Logic Analyzer

Visualize, measure, and analyze transitions and states over time

Topics

Overview

Data Capture Workflow
High-level steps for capturing signal data from a design running on an FPGA.

Data Capture Requirements and Preparation

Download FPGA Board Support Package
The FPGA board support packages contain the definition files for all the supported boards for FPGA-in-the-loop (FIL) simulation, FPGA data capture, or AXI manager.
Set Up FPGA Design Software Tools
Set the MATLAB path to Xilinx, Microchip, and Intel software.
Guided Hardware Setup
Describes the steps in the automated support package setup process for configuring hardware for use with FPGA-in-the-loop, AXI manager, or FPGA data capture.
Configure Logic Analyzer
Adjust settings in the Logic Analyzer.

Featured Examples

Debug IP Core Using FPGA Data Capture

Debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.

Capture Temperature Sensor Data from Xilinx FPGA Board Using FPGA Data Capture

Use FPGA data capture with existing HDL design to capture FPGA internal signals over a JTAG or Ethernet connection. Start with an existing FPGA design that implements Xilinx® XADC IP to read the on-chip temperature sensor data. The XADC IP exposes a dynamic reconfiguration port (DRP) interface for read and write internal registers. This FPGA design contains logic that reads out the temperature sensor register from the XADC IP. To obtain the temperature reading for further analysis, use the FPGA data capture feature to read the raw sensor data into the MATLAB® workspace. Then, MATLAB converts the raw temperature data to Celsius.

Open Script

Stream Audio Signal from Intel FPGA Board Using Ready-to-Capture Signal

Use a ready-to-capture signal in an FPGA data capture with existing HDL code to read FPGA streaming signals. This example starts with an existing FPGA design that implements an on-chip analog-to-digital converter (ADC) to sample an audio signal. The ADC intellectual property (IP) exposes an Avalon® memory-mapped (MM) slave interface for control and an Avalon streaming interface for data output. The existing example contains a simple Avalon MM master to start the ADC. Use FPGA data capture to collect the ADC output data from the Avalon streaming interface and stream the data to the MATLAB® workspace.

Open Script

Debug YOLO v2 Vehicle Detector on FPGA

Debug a vehicle detector design by viewing internal signals while the design is deployed on a board.

Verify OFDM Transmit and Receive using FPGA Data Capture

Debug, visualize, and analyze the internal signals of a wireless HDL IP while you run the complete design on hardware.

Open Script