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Create a Custom Hardware Platform

Integrate generated IP core into a target SoC device, Speedgoat® I/O module, or standalone FPGA board by defining a custom board and reference design

HDL Coder™ supports a limited number of pre-existing target platforms. For rapid prototyping, a pre-existing board works, but for production, a custom platform is typically required. Create a custom platform to integrate the IP core into a standalone FPGA board or SoC platform with Xilinx® Vivado® IP Integrator or Intel® Qsys.

You can create your own custom reference design in MATLAB® and use HDL Coder to integrate the IP core into your reference design.

For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.

Create a custom hardware platform workflow

Classes

hdlcoder.BoardBoard registration object that describes SoC custom board
hdlcoder.ReferenceDesignReference design registration object that describes SoC reference design

Functions

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addCustomEDKDesignSpecify Xilinx EDK MHS project file
addCustomQsysDesignSpecify Altera Qsys project file
addCustomVivadoDesignSpecify Xilinx Vivado exported block design Tcl file
addCustomLiberoDesignSpecify Microchip Libero SoC exported block design Tcl file (Since R2022b)
addIPRepositoryInclude IP modules from your IP repository folder in your custom reference design
addParameterAdd and define custom parameters for your reference design
validateReferenceDesignCheck property values in reference design object
validateBoardCheck property values in board object
addEthernetMACInterface Define Ethernet MAC interface for board object (Since R2022b)
addExternalIOInterfaceDefine external IO interface for board object
addExternalPortInterfaceDefine external port interface for board object
addInternalIOInterfaceAdd and define internal IO interface between generated IP core and existing IP cores
addAXI4MasterInterfaceAdd and define AXI4 Master interface
addAXI4SlaveInterfaceAdd and define AXI4 slave interface
addAXI4StreamInterfaceAdd AXI4-Stream interface (Since R2020a)
addAXI4StreamVideoInterfaceAdd AXI4-Stream Video interface (Since R2020a)
addClockInterfaceAdd clock and reset interface
addMemoryInterfaceAccess memory regions on your FPGA or SoC hardware (Since R2023a)
CallbackCustomProgrammingMethodFunction handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
CustomizeReferenceDesignFcnFunction handle for callback function that gets executed before Set Target Interface task in the HDL Workflow Advisor (Since R2020a)
EmbeddedCoderSupportPackageSpecify whether to use an Embedded Coder support package
PostBuildBitstreamFcnFunction handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
PostCreateProjectFcnFunction handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
PostSWInterfaceFcnFunction handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
PostTargetInterfaceFcnFunction handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
PostTargetReferenceDesignFcnFunction handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor
addDeviceTreeAdd device tree for board object (Since R2021b)
addDeviceTreeIncludeDirectorySpecify the path of an include file to compile the device tree against (Since R2021b)
addDeviceTreeAdd device tree for reference design object (Since R2021b)
addDeviceTreeIncludeDirectorySpecify the path of an include file to compile the device tree against (Since R2021b)
socExportReferenceDesignExport custom reference design for HDL Workflow Advisor (Since R2020a)

Topics

Board and Reference Design

Specific Hardware Platforms

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.