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HDL-Optimized Filters and Transforms

Choose blocks or System objects to create HDL-optimized hardware system designs

These DSP HDL Toolbox™ blocks and System objects implement hardware-friendly architectures and support HDL code generation when used with HDL Coder™. These blocks and System objects also have high-throughput streaming interfaces, hardware control signals, and options to select different hardware implementations of their algorithms.

Blocks

FFT	Compute fast Fourier transform (FFT)
IFFT	Compute inverse fast Fourier transform (IFFT)
Channelizer	Polyphase filter bank and fast Fourier transform
Channel Synthesizer	Combine narrowband signals into multichannel signal (Since R2022a)
Discrete FIR Filter	Finite-impulse response filter
Biquad Filter	Biquadratic IIR (SOS) filter (Since R2022a)
LMS Filter	Minimize error between observed and desired signals (Since R2023a)
Farrow Rate Converter	Polynomial sample-rate converter (Since R2022a)
FIR Decimator	Finite impulse response (FIR) decimation filter (Since R2020b)
FIR Interpolator	Finite impulse response (FIR) interpolation filter (Since R2022a)
CIC Decimator	Decimate signal using CIC filter (Since R2019b)
CIC Interpolator	Interpolate signal using CIC filter (Since R2022a)
FIR Rate Converter	Upsample, filter, and downsample input signal
NCO	Generate real or complex sinusoidal signals
Complex to Magnitude-Angle	Compute magnitude and phase angle of complex signal using CORDIC algorithm
Downsampler	Downsample by removing data samples between input samples (Since R2022b)
Upsampler	Upsample by adding zeros between input samples (Since R2022b)

Objects

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Filters and Transforms

`dsphdl.FFT`	Compute fast Fourier transform (FFT)
`dsphdl.IFFT`	Compute inverse fast Fourier transform (IFFT)
`dsphdl.Channelizer`	Polyphase filter bank and fast Fourier transform
`dsphdl.ChannelSynthesizer`	Combine narrowband signals into multichannel signal (Since R2021b)
`dsphdl.FIRFilter`	Finite-impulse response filter
`dsphdl.BiquadFilter`	Biquadratic IIR (SOS) filter (Since R2022a)
`dsphdl.LMSFilter`	Minimize error between observed and desired signals (Since R2023a)
`dsphdl.FarrowRateConverter`	Polynomial sample-rate converter (Since R2022a)
`dsphdl.FIRDecimator`	Finite impulse response (FIR) decimation filter (Since R2020b)
`dsphdl.FIRInterpolator`	Finite impulse response (FIR) interpolation filter (Since R2022a)
`dsphdl.CICDecimator`	Decimate signal using CIC filter (Since R2019b)
`dsphdl.CICInterpolator`	Interpolate signal using CIC filter (Since R2022a)
`dsphdl.FIRRateConverter`	Upsample, filter, and downsample input signal
`dsphdl.NCO`	Generate real or complex sinusoidal signals
`dsphdl.ComplexToMagnitudeAngle`	Magnitude and phase angle of complex signal
`dsphdl.Downsampler`	Downsample by removing data samples between input samples (Since R2022b)
`dsphdl.Upsampler`	Upsample by adding zeros between input samples (Since R2022b)

Topics

High-Throughput HDL Algorithms
Choose a block that supports frame-based processing for HDL code generation.
Hardware Control Signals
Hardware control signals such as valid and reset used by DSP HDL Toolbox blocks.
FIR Filter Architectures for FPGAs and ASICs
Learn how DSP HDL Toolbox blocks implement hardware-friendly filter architectures.
Control Data Rate Using Ready Signal
Implement backpressure and regulate output rate in an interpolator system.

Featured Examples

Gigasamples-per-Second Correlator and Peak Detector

Implement a high-throughput correlator and peak detector suitable for LiDAR and mm-wave RADAR applications on FPGA.

Open Script

NFC Digital Downconverter

Design a high rate-change factor DDC for near-field communications systems on FPGAs.

Open Script

High Performance DC Blocker for FPGA

Create a DC blocking filter for a hardware communications system.

Open Script

HDL Implementation of LMS Filter

Implement a fully-serial least mean square (LMS) adaptive filter algorithm.

Open Script

Frequency-Domain Filtering in HDL

Implement a filter in the frequency domain.

Open Script

Partly Serial Systolic FIR Filter Implementation

Implement a 32-tap lowpass FIR filter that shares multiplier resources within the filter.

Open Model

Fully Parallel Systolic FIR Filter Implementation

Implement a 25-tap lowpass FIR filter.

Open Model

Programmable FIR Filter for FPGA

Implement a programmable FIR filter for hardware. You can program the filter to the required response by loading the coefficients into internal registers using a memory-style interface.